Cmos Sram Circuit Design and Parametric Test in Nano-scaled Technologies (Hardcover)

• Category:  Books  »  Engineering & Technology  »  Electronics - Circuits - General
• Format: Hardcover   Learn more about the Hardcover format using Tower WIKI.
• Number of Pages: 200
• ISBN: 1402083629
• WAPI (Tower ID): 112078364
• Release Date: June 1, 2008
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• Tower.com Sales Rank: #517664 in Books (See Top 100 Books Bestsellers)
• #6512 in Engineering & Technology (See Top 100 Engineering & Technology Bestsellers)
• #114 in Electronics - Circuits - General (See Top 100 Electronics - Circuits - General Bestsellers)

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As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions.

Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired.

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.

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